Abstract:
The SHIP project is creating access to Intel’s state-of-the-art packaging to the US Government’s contractors, and about developing interface and security technology to facilitate the use of chiplet architectures. This talk will describe research and engineering topics in development for SHIP by the Intel Programmable Solutions Group (PSG) CTO Office.
Event Details:
Topic: Research and Engineering for the State-of-the-art Heterogeneous Integrated Packaging (SHIP) Project
Presented by: David C. Kehlet, Research Scientist, Intel
Date: Friday, June 16, 2023
Time: 1pm – 2:30pm EST
Location: Larsen Hall, Room 310 & Zoom
Zoom Link: https://ufl.zoom.us/j/98046182737?pwd=a3JlTWpEYVc5Tk5HOHYvUmt5NTRQQT09
Meeting ID: 980 4618 2737
Passcode: 214382
Hosted By: Dr. Swarup Bhunia
Bio:
David Kehlet is a researcher at Intel working on pathfinding for programmable logic technologies. David is currently developing chiplet technologies to enable a new model of electronic system development, and is Principal Investigator of the US Government’s State-of-the-art Heterogeneous Integrated Packaging (SHIP) Chiplet Design Technologies project. Earlier at Intel, David was Vice President of IP Engineering, developing SERDES chiplets, communications protocols, signal processing, and memory interfaces on Intel’s programmable logic devices. David’s team developed the FPGA industry’s first HBM2 enabled device and the first FPGA with 56Gbps SERDES. David earned BS and MS Electrical Engineering degrees from Stanford University and holds 19 patents.