The Warren B. Nelms Institute for the Connected World
presents:

“Quantum Computing: Synthesis Challenges and Impact on IoT Security”
Thursday, July 11 @ 11am
234 Larsen Hall

Participate remotely with Zoom: https://ufl.zoom.us/j/474271512

Abstract

More than half a century after quantum mechanics was accepted as a more accurate model of atomic physics, Richard Feynman proposed in 1981 the brilliant vision of building computers based on quantum mechanical systems. While significant speed-up of quantum algorithms over classical ones for certain problems have been proved in the ‘90s, notable progress in the technology of quantum computers has been recent. The focus of this talk is on the methodologies for logic and physical synthesis of quantum computing circuits taking fault tolerance and error-correction into account. The efficiency of these methods are expressed in terms of the quantum resources needed and also the number of cycles of operations. The possible trade-offs in the design flow and also the impact on design of secure IoTs are also discussed briefly.

Biography

Susmita Sur-Kolay received the B.Tech.(Hons.) degree in Electronics and Electrical Communications Engineering from Indian Institute of Technology Kharagpur and the Ph.D. degree in Computer Science and Engineering from Jadavpur University India. She has been a faculty member in the Advanced Computing and Microelectronics Unit of the Indian Statistical Institute, Kolkata, India since 1999 and is presently a Professor. During the period 1993-99, she was a Reader in the Department of Computer Science and Engineering of Jadavpur University. Prior to that, she was a post-doctoral fellow at University of Nebraska-Lincoln, and a Research Assistant at the Laboratory for Computer Science in Massachusetts Institute of Technology. She was also on sabbatical at Princeton University and Intel Corp., USA. Her research contributions are in the areas of electronic design automation for VLSI physical design, fault modeling and testing, synthesis of quantum computers, and graph algorithms. She has co-authored several technical papers in leading international journals and refereed conference proceedings, and a chapter in the Handbook on Algorithms for VLSI Physical Design Automation. She was the Technical Program Co-Chair of the 18th International Conference on VLSI Design (2005),the 11th Symposium on VLSI Design and Test (2007), ISVLSI 2011 and has served on the program committees of several international conferences. She has served on the editorial board of the IET Computers and Digital Techniques, and IEEE Transactions on VLSI Systems. She is a Distinguished Visitor of IEEE Computer Society (India), Senior Member of IEEE, Member of ACM, IET and VLSI Society of India. Among other awards, she was the recipient of the President of India Gold Medal (summa cum laude) at IIT Kharagpur (1980), IBM Faculty Award (2009).